Arm Hiring 2026: Engineer – Memory Layout | Bengaluru (Job ID 2026-19042)

Company: Arm
Job Title: Engineer – Memory Layout / Memory Design
Job Requisition ID: 2026-19042
Category: Hardware Engineering / Physical IP Division
Work Arrangement: Hybrid Working Pattern
Employment Type: Full-Time
Posted Date: September 1, 2026
Experience Level: 2–5 Years
Location: Bengaluru, Karnataka, India

Arm is a global leader in processor architecture and semiconductor IP, powering billions of chips across mobile, cloud data centers, automotive, and IoT applications.

The Engineer – Memory Layout role operates within Arm’s Physical IP Division in Bengaluru. In this position, engineers work on high-performance SRAMs, fast cache instances, and register files targeted at cutting-edge foundry nodes, including 14A and 2nm. The role spans design, layout, margining, characterization, verification, and automated view generation (GDS, LEF, Liberty, Verilog) to deliver low-power, high-density Memory IP used by SoC designers globally.

• Memory IP Development: Design, margin, characterize, and verify various memory instances (Single-Port/Dual-Port SRAMs, Register Files).
• View Generation & Delivery: Produce and validate industry-standard design views including Verilog models, Liberty (.lib) timing/power models, schematics, LEF (Library Exchange Format), and GDSII physical layouts.
• Advanced Technology Integration: Work with leading foundry process design kits (PDKs) on advanced sub-2nm nodes (e.g., 14A, 2nm) for high-speed, low-power applications.
• EDA Tool Workflows: Utilize industry-standard electronic design automation (EDA) tools for layout design, physical verification (DRC, LVS, PERC), and characterization.
• Automation & AI Integration: Write custom scripts (TCL, Shell, Python) and leverage AI/ML tools to accelerate development flows and automate repetitive QA/verification tasks.

Academic Qualification

• Bachelor’s or Master’s Degree in Electronics Engineering, Microelectronics, VLSI Design, or a related discipline with strong academic credentials.

Technical & Professional Experience

• Experience: 2 to 5 years of hands-on experience in memory layout, memory design, or memory characterization.
• Circuit & Device Fundamentals: Deep understanding of SRAM bitcell operation, sense amplifiers, decoders, digital circuit fundamentals, semiconductor device physics, and SoC integration concepts.
• Scripting & Automation: Strong working knowledge of Shell and TCL scripting; exposure to AI-driven workflows in EDA design.
• Desirable Knowledge: Basic understanding of Computer Architecture and cache organization.

• Estimated Base Salary: ₹14 LPA to ₹22 LPA (CTC range based on experience level and technical assessment).
• Workplace Flexibility: Hybrid model with team-led flexibility for office vs. remote days.
• Corporate Benefits:
  • Comprehensive health insurance, wellness coverage, and employee assistance programs.
  • Access to internal learning portals, technical training, and EDA tool certifications.
  • Disability and interview accommodation support (accommodations@arm.com).

1. Resume Screening
   (Verification of 2-5 yrs memory design/layout experience, SRAM background, & scripting skills)
   ↓
2. Technical Telephonic / Screening Round
   (Focus on SRAM basic operation, 6T bitcells, read/write margins, device physics, & logic gates)
   ↓
3. Core Technical Interview - Round 1 (Circuit & Layout Focus)
   (Deep dive into memory layouts, DRC/LVS, LEF/GDS generation, timing views, & parasitic extraction)
   ↓
4. Core Technical Interview - Round 2 (Characterization & Scripting)
   (Evaluation of Liberty models, timing/power characterization, TCL/Shell scripting, & automation)
   ↓
5. Managerial & Culture Fit Round
   (Discussion on team collaboration, problem-solving, hybrid expectations, & growth)
   ↓
6. HR Discussion & Formal Offer

• SRAM Architecture & Bitcell Operation: Read/write operation of 6T SRAM cells, static noise margin (SNM), hold margin, write assist, and sense amplifier topologies.
• Physical Layout & Nanometer Effects: DRC, LVS, antenna rules, electro-migration (EM), IR drop, parasitic extraction (RC), and advanced node rules (FinFET, GAA/GNS at 2nm/14A).
• Memory Views & Delivery: Differences and generation methods for LEF, GDSII, Liberty (.lib), Verilog netlists, and CDL schematics.
• EDA Scripting: TCL commands for layout/characterization tools and Shell scripting for automated regression runs.

• Memory & Physical IP: Memory Layout, SRAM Design, Single-Port SRAM, Dual-Port SRAM, Register File, Bitcell, Sense Amplifier, Fast Cache, Physical IP
• Foundry & Nodes: 2nm, 14A, FinFET, GAAFET, Advanced Technology Nodes, High-Density SRAM, Low-Power Design
• EDA Views & Verification: DRC, LVS, LEF, GDSII, Liberty (.lib), Verilog, Schematic, Parasitic Extraction (PEX), Characterization, Margining
• Scripting & Tools: TCL, Shell Scripting, Python, EDA Automation, AI in EDA

1. What is the Job Requisition ID for this role?

The official job ID is 2026-19042.

2. Where is this job located?

The position is based in Bengaluru, India, under Arm’s Hybrid working model.

3. What experience level is Arm looking for?

Candidates with 2 to 5 years of experience in memory design, layout, or characterization are eligible to apply.

4. What technology nodes will this role work on?

The role focuses on memory IP for advanced nodes, specifically 14A and 2nm from leading semiconductor foundries.