Qualcomm Hiring 2027: Hardware Engineer – Campus Graduate | Bangalore (Job ID 3094020)

Company: Qualcomm India Private Limited
Job Title: 2027 Campus Hire_ Engineer_ HW
Job ID / Requisition: 3094020
Job Area / Group: Engineering Group > Hardware Engineering
Employment Type: Full-Time (Campus Graduate / Entry Level)
Target Graduation Batch: 2027 Batch (B.E. / B.Tech / M.E. / M.Tech)
Location: Bangalore (Bengaluru), India (+1 additional location in India)

Qualcomm is a global technology pioneer in wireless communications, semiconductor design, Snapdragon system-on-chips (SoCs), edge AI, and mobile connectivity. The Hardware Engineering Group at Qualcomm powers the physical architecture driving modem, multimedia, connectivity, autonomous driving, and computer vision acceleration.

As a 2027 Campus Hire Hardware Engineer, you will contribute directly to next-generation silicon development. Depending on team matching and specialization, hardware campus hires work across core VLSI domains including RTL Design, SoC Verification, Physical Design, RF/Analog/Mixed-Signal IC Design, Design for Testability (DFT), CPU Design, and FPGA Prototyping.

Campus hires are aligned with specialized hardware development tracks within Qualcomm’s SoC units:

• Digital ASIC & RTL Design: Write clean, synthesizable Verilog/SystemVerilog code for modem, multimedia, or computer vision acceleration blocks.
• Design & SoC Verification: Construct UVM-based testbenches, run coverage-driven constrained random verification, and debug RTL regressions using SystemVerilog and C/C++.
• SOC & Hard Macro Physical Design: Execute synthesis, floorplanning, placement and routing (P&R), clock tree synthesis (CTS), static timing analysis (STA), and DRC/LVS physical signoff.
• RF, Analog & Mixed-Signal IC Design: Design and simulate high-frequency RF circuits, LNAs, PLLs, ADCs/DACs, and power management ICs (PMIC) using Cadence and SpectreRF toolchains.
• Design for Testability (DFT): Implement scan chains, MBIST (Memory Built-In Self-Test), JTAG, and ATPG patterns for silicon manufacturing testability.
• SOC Validation & Board/FPGA Design: Emulate hardware blocks on high-end FPGA platforms, run silicon bring-up in labs, and perform logic analyzer debugging.

Academic Background

• Degree: Bachelor’s (B.E. / B.Tech) or Master’s (M.E. / M.Tech / MS) degree in Electrical Engineering, Electronics & Communication Engineering (ECE), VLSI Design, Embedded & VLSI, Computer Engineering, or related fields.
• Graduation Year: Target campus hiring batch graduating in 2027.

Mandatory Technical Skills

• Hardware Description Languages: Hands-on proficiency in Verilog or VHDL; exposure to SystemVerilog or UVM is highly preferred.
• Programming & Scripting: Strong coding skills in C/C++ and scripting in Tcl, Perl, or Python/Shell.
• VLSI & Digital Fundamentals: Solid grasp of Digital Logic Design, Finite State Machines (FSM), Static Timing Analysis (STA), CMOS logic, and Computer Architecture.
• Analog Track Requirements (For Analog/RF applicants): Understanding of PLLs, LNAs, OpAmps, ADC/DAC architectures, and Cadence Spectre/SpectreRF tools.

• Estimated Starting Salary: ₹16 LPA to ₹24 LPA (CTC) for fresh campus hardware hires (varies between Bachelor’s and Master’s/VLSI specialization degrees), plus RSU stock grants and performance bonuses.
• Corporate Benefits:
  • Comprehensive Health, Term Life, and Personal Accident Insurance.
  • Access to cutting-edge EDA tool suites (Cadence, Synopsys, Siemens EDA) and silicon bring-up labs.
  • Structured internal learning tracks, patent filing incentives, and global technical conferences.

1. Campus Resume Shortlisting & Registration (Job ID: 3094020)
   (Verification of 2027 graduation batch, ECE/VLSI/EEE degree, & academic performance)
   ↓
2. Online Campus Technical Assessment (Domain Specific)
   (Evaluation of Digital Logic Design, CMOS, STA, C/C++ programming, Verilog code snippets, & Aptitude)
   ↓
3. Technical Interview Round 1 (Digital Logic & RTL / Analog Concepts)
   (Deep dive into FSMs, setup/hold time timing analysis, clock domain crossing [CDC], & Verilog coding)
   ↓
4. Technical Interview Round 2 (Domain Specialization & Hardware Debugging)
   (Questions on academic projects, chip verification/UVM, physical design flows, or analog circuit simulation)
   ↓
5. HR Discussion & Campus Offer Rollout

• Digital Design & STA: Setup time, hold time, max frequency calculation, clock skew, jitter, Metastability, Clock Domain Crossing (CDC), multi-cycle paths, and asynchronous FIFOs.
• RTL & Scripting: Blocking vs. non-blocking assignments in Verilog, writing testbenches, TCL scripting for EDA tools, and Python data manipulation.
• Computer Architecture: RISC-V / ARM architecture basics, pipelining, cache coherence, memory hierarchies, and bus protocols (AMBA AXI/AHB/APB).

• VLSI & Hardware Design: Hardware Engineering, RTL Design, SoC Design, Verilog, VHDL, SystemVerilog, UVM, Digital ASIC Design, Physical Design, Synthesis
• Verification & Testing: Design Verification, System Verification, Static Timing Analysis (STA), Design for Test (DFT), Scan Chain, MBIST, ATPG, FPGA Prototyping
• Analog & RF: Analog Design, RF IC Design, Mixed-Signal, PLL, LNA, ADC, DAC, Cadence Virtuoso, SpectreRF, CMOS
• Programming & Automation: C++, C, TCL Scripting, Perl, Python, Shell Scripting, Computer Architecture

1. What is the Job ID for this hardware engineering opening?

The official Qualcomm Job Requisition ID is 3094020.

2. Which academic streams are targeted for this campus drive?

Candidates pursuing a Bachelor’s or Master’s in Electrical Engineering, ECE, VLSI Design, or Embedded Systems graduating in 2027 are eligible.

3. What hardware domains are covered under this requisition?

This drive hires across multiple hardware teams, including Digital ASIC Design, SoC Verification, Physical Design, Analog/RF IC Design, DFT, and CPU Design.

4. Where is the job located?

The primary engineering location is Bangalore (Bengaluru), India, with potential allocation to secondary R&D centers in India.